This disclosure relates generally to the field of computer hardware, and more particularly to successive approximation analog to digital converters.
Analog-to-digital converters (ADCs) are circuits that convert a signal in analog format to a signal in digital format. Successive approximation ADCs (SA-ADC) may be used for relatively low-speed applications. SA-ADCs have high accuracy, a small footprint, and relatively low power consumption. An SA-ADC functions by comparing the analog signal that is being converted (Vin) to a guessed analog voltage (Vguess) that is generated by a digital to analog converter (DAC) in the SA-ADC based on a digital code. Through successive passes, Vguess gets closer to Vin, and at the final pass the digital code that creates Vguess is given as a result that is a digital approximation of Vin.
An example of an SA-ADC according to the prior art is shown in FIG. 1. Reference generator 101 includes a digital to analog converter (DAC) 102. The reference generator provides Vin 108 to the comparator 103. The DAC 102 in reference generator 101 generates Vguess 107 based on input from logic 104. Logic 104 starts with all bits in a result set (which is a set of N bits) set to zero. First, the logic 104 sets the most significant bit in the result set (bit N) to 1, and sends the result set to the DAC 102 via digital inputs 106. The DAC 102 generates Vguess 107 based on the digital input 106, and provides Vguess 107 to the comparator 103. The comparator 103 indicates to the logic 104 whether Vguess 107 is greater than or less than Vin 108 via signal 109. If Vguess 107 is determined to be greater than Vin 108 by the comparator 103, the most significant bit in the result set is set back to zero by logic 104; otherwise, the most significant bit is left as one. The logic 104 then steps through each bit in the result set as described above, from bit N−1 to the least significant bit. At each clock cycle of clock 105, the logic 104 determines one more bit of the result set based on feedback from signal 109 from the comparator 103, and after N clock cycles, the final result set is sent to the output 110 by the logic 104.
An SA-ADC may have errors in the output due to comparator offset, DAC error, and/or reference voltage error. Some solutions to comparator offset include addition of offset correction circuitry or differential signaling to the SA-ADC. However, offset correction circuitry requires additional power for the SA-ADC circuit and a larger footprint, while differential signaling requires more complex circuitry and access to differential reference voltages, which may not be easily obtained on-chip. Additionally, offset correction or differential signaling circuitry may require a negative power supply, which may be absent in processor chips.